1. Field of the Invention
The present invention relates to a method of transferring data through a bus and a bus master control device used in an information processing unit.
2. Description of the Related Art
A DMA (Direct Memory Access) controller is a control device used for performing high-speed data transfers directly between peripheral units (e.g., a memory, an I/O (Input/Output) device) connected to a common bus without involving the CPU.
FIGS. 5A to 5D are schematic diagrams each illustrating a conventional data transfer method using a DMA controller with each hexagonal block representing a single data transfer operation (e.g., a data transfer operation performed for a single word in one cycle). The data transfer operations are performed successively from left to right in the figures. The bus master at each data transfer operation is indicated inside the corresponding block. A bus master is a device which is controlling the current data transfer while occupying the bus. For example, the CPU or the DMA controller may be a bus master. In FIGS. 5A to 5D, the label “DMA” indicates that the DMA controller is occupying the bus as the bus master at the time, whereas “Other” indicates that a bus master other than the DMA controller (e.g., the CPU) is occupying the bus as the bus master at the time.
FIG. 5A illustrates the “burst-mode transfer method” where the bus remains occupied by the DMA controller from activation of a DMA transfer operation to completion of the DMA transfer operation. Accordingly, during burst-mode transfer operations, another device (e.g., the CPU) must wait for a long time until the DMA transfer is completed before it may serve as the bus master and transfer data to and from the memory through the bus. In order to eliminate this long wait during burst-mode transfer operations, there have been proposed other data transfer methods as shown in FIGS. 5B, 5C and 5D.
FIG. 5B illustrates a “word-by-word transfer method” wherein the bus master occupying the bus is forcibly switched between the DMA controller and another device after each one-word data transfer. FIG. 5C illustrates a “cycle-steal transfer method” where the DMA controller serves as the bus master for DMA transfers only when the bus is not occupied by the other device serving as the bus master. FIG. 5D illustrates a “timer interruption transfer method” where the bus master occupying the bus is switched between two devices by interrupts generated at predetermined intervals based on a timer. In the timer interruption transfer method, the DMA controller performing a DMA transfer is forced to discontinue the DMA transfer when the interrupt is generated after a predetermined period of time. The predetermined period of time runs from the activation of the DMA transfer. Once the DMA transfer is forced to discontinue, the other device serves as the bus master and occupies the bus. When another interrupt is generated after the predetermined time, the other device is forced to discontinue serving as the bus master and release the bus so that the DMA controller again can serve as the bus master and resume the interrupted DMA transfer.
For data transfers (e.g., DMA transfers) in a system where a plurality of devices which can serve as bus masters share a common bus, there has been a demand for improving the transfer efficiency for both the DMA controller and the other devices.
In the “word-by-word transfer method”, however, the DMA transfer operations cannot be performed successively. Therefore, this method cannot be used to access a memory employing a high-speed transfer mode (e.g., the page mode of a DRAM). This results in a very poor DMA transfer efficiency.
In the “cycle-steal transfer method”, besides the above-noted problem, the other devices serving as bus masters may occupy the bus for a long time during which the DMA controller cannot access the bus. In such a case, the DMA controller has to wait for a long time until it is allowed to perform a DMA transfer and, therefore, the DMA transfer may not be completed within a predetermined period of time.
In the “timer interruption transfer method”, a first device currently serving as the bus master (i.e., occupying the bus) is forcibly switched to a second device (to act as the bus master) upon a timer-based interrupt even at an undesirable time for the first device currently occupying the bus. This also results in a poor data transfer efficiency.